The present disclosure herein relates to a phase locked loop (PLL), and more particularly to, a PLL for reducing fractional spur noise.
In recent, a charge pump and a phase locked loop (PLL) are being mostly used for implementing a radio frequency (RF) synthesizer for multi-band mobile communication. However, the charge pump PLL is integrated with an analog circuit design technology and needs, due to an analog circuit and analog signal characteristics, an extra analog RF library in addition to a design library that provides in a standard digital CMOS process. Thus, the charge pump PLL has a difficulty in integrating with a digital baseband signal processing block that uses a digital CMOS process. Also, the digital baseband signal processing block is being recently developed by a nano-scale digital CMOS process due to a development in process technology.
As such, with a development in nano technology, a digital circuit may easily adapt to a process technology to be manufactured in many cases even without re-designing, but the analog RF circuit has a limitation in that it needs to be re-designed each time the process technology varies. Also, with a nano-scale development in CMOS process technology, there is a drawback in that an operating voltage also decreases.
In the nano-scale digital CMOS process, a lot of time and a lot of costs are being consumed in order to improve many limitations that appear when designing the analog RF circuit. Thus, research and development in digital RF for gradually digitalizing the analog RF circuit block are being actively performed.